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dc.contributor.advisorJohnson, Taylor
dc.creatorLong, Randy Kyle
dc.date.accessioned2016-10-25T19:44:30Z
dc.date.available2016-10-25T19:44:30Z
dc.date.created2016-08
dc.date.issued2016-08-26
dc.date.submittedAugust 2016
dc.identifier.urihttp://hdl.handle.net/10106/26134
dc.description.abstractThis document presents a design method and example for a time-triggered CAN (TTCAN) system which reduces latency, variability in transmission frequency, and increases data throughput relative to the traditional free-for-all CAN (FFACAN) transmission system. In addition to performance considerations for a TTCAN transmission scheme, this document also presents a simple method for measuring CPU usage on embedded systems that use either nested or non-nested interrupts. Systems that use non-nested interrupts may have their performance measured with a single GPIO pin; systems that use nested interrupts require one pin per interrupt service routine.
dc.format.mimetypeapplication/pdf
dc.subjectController Area Network, Time Division Multiple Access, Formula SAE, CPU performance, interrupts CAN, TDMA, FSAE
dc.titleTime-Triggered Controller Area Network Design for Formula SAE Racecars and Technique for Measuring CPU Usage on Systems with Nested and Non-Nested Interrupts
dc.typeThesis
dc.date.updated2016-10-25T19:45:01Z
thesis.degree.departmentElectrical Engineering
thesis.degree.grantorThe University of Texas at Arlington
thesis.degree.levelMasters
thesis.degree.nameMaster of Science in Electrical Engineering
dc.type.materialtext
dc.creator.orcid0000-0002-0579-2110


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