| dc.description.abstract | Nowadays, the packaging of electronic products is becoming revolutionized, since the packages are becoming more and more complex, dense, thinner and lighter for greater portability. Miniaturization of packages is being taken to the next level, and hence, 3D packaging has become a hot topic in the present research area. Three dimensional chips stacking with TSV technology has gained momentum to meet such requirements of significant miniaturization and power reduction which result in increased performance. However, the unique issues related to yield and reliability of critical areas in TSV based 3D ICs need to be evaluated. Therefore, Reliability of such electronic packages has become a critical issue in today’s technological scenario. In this study, the 3D package has been subjected to reflow process and the resultant modes of fracture prevalent along the length of the TSV due to the CTE mismatch between different materials has been identified. Design changes in the die and substrate thickness has been simulated to study its affect on the crack driving energy. Analysis is done using Finite Element Method (FEM) to obtain the stress intensity factor (SIF) in the TSV region as well as the stress distribution in solder joints for different die size and substrate thickness, thereby trying to address and predict the prevalent modes of fracture in TSV and assist in the design changes to reduce failure probability. | |
