Development Of Three Block Thermal Compact Model And Verification Of Modified Linear Superposition Technique For Stacked Die

Abstract

Over the last few years an impressive amount of progress has been achieved in the field of compact modeling of chip packages. But available compact modeling methods could not address the issue of limitation on the mesh statistics which is major concern while modeling in FEM softwares with limited number of nodes and elements. It is not possible to attain convergence of solution for thermal simulation of detailed model with the constraint on the number of nodes and elements. In this thesis, a simple and straight forward three block (3B) compact modeling method is developed. 3B compact modeling method has been implemented for numerous packages for verification of modified linear superposition technique and concluded that modified linear superposition technique is a good option for thermal characterization of stacked die with reduced modeling and simulation efforts and utilizing limited set of data from the standard thermal test.